EP80579 Datasheet, PDF (327/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 12-13.Source in Memory Initialization and Destination in Increment Mode Transfer
MSB
Memory
LSB
A5
A5
64-bit Destination
A5
Programmed Values
EDMACTL 0000 0088H
SUAR/SAR A581 BCE6H
DUAR/DAR
TCR
DCR
4001 0307H
0000 0014H
0000 201FH
81 BC E6 A5
81 BC E6 A5
81 BC
81 BC
81 BC
XX
value
Bus operation
DESTINATION
Byte store@ 40010307
QWORD store@ 40010308
QWORD store@ 40010310
3-Byte store@ 40010318
4001 0300H
E6 _{4001 0308H}
E6 _{4001 0310H}
E6 _{4001 0318H}
12.5.2.4.2 Buffer Initialization Mode
Buffer initialization mode transfers will logically only be to memory mapped I/O and will
utilize the constant destination mode and granularity fields of the DCR. The address
granularity is dictated by the granularity field in the DCR. No errors will be flagged if
the destination address is not matched to the granularity, but the required lower
address bits will be ignored.
Figure 12-14 though Figure 12-16 illustrate buffer initialization mode to an arbitrary
destination address.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
327