EP80579 Datasheet, PDF (766/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.2.1
20.2.1.1
Register Descriptions
Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address Registers
for Channels 0-3
Table 20-4. Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address
Registers for Channels 0-3
Description: Ch. 0: 00h - 10h; Ch.1: 02h - 12h; Ch.2: 04h - 14h; Ch.3: 06h - 16h
View: IA F
Base Address: 0000h (IO)
Size: 16 bit^a
Default: XXXX
Offset Start: 00h at 02h
Offset End: 10h at 02h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
15 : 00
BCADD
Base and Current Address: This register determines the
address for the transfers to be performed. The address
specified points to two separate registers. On writes, the
value is stored in the Base Address register and copied to
the Current Address register. On reads, the value is
returned from the Current Address register.
The address increments/decrements in the Current
Address register after each transfer, depending on the
mode of the transfer. If the channel is in auto-initialize
mode, the Current Address register is reloaded from the
Base Address register after a terminal count is generated.
For transfers to/from a 16-bit slave (channels 5-7), the
address is shifted left one bit location. Bit 15 is shifted into
bit 16.
The register is accessed in 8-bit quantities. The byte is
pointed to by the current byte pointer flip/flop. Before
accessing an address register, the byte pointer flip/flop
must be cleared to ensure that the low byte is accessed
first.
XXXX
RW
a. This register provides an 8-bit window into a 16-bit quantity. The byte accessed depends on the current byte pointer flip/flop.
Intel^® EP80579 Integrated Processor Product Line Datasheet
766
August 2009
Order Number: 320066-003US