EP80579 Datasheet, PDF (1419/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.5.12.3 Internal Memories
The internal memories are protected via various means to reduce the SER associated
with this unit. All memories must be scrubbed to ensure proper operation.
The GbE ECC/parity protected memories indicated in Figure 37-49 may be tested with
the Memory Error Test Register (MET). The register will force an error to be written into
the memory area selected with the MET.SELECT field. The MET.MASK field will be XOR’d
with the ECC or parity bits to insert a parity error into the selected memory, which will
cause an error when the memory is read at a later time. Errors will be reported in the
appropriate bits of the three ICR registers. Functional or Error interrupt(s) may be
generated if enabled.
Figure 37-49.Memory Protection in the GbE
ECC
Statistic
Registers
ECC
RX Descr
Buffer
Parity
RX
Filter
CRC
checked
here
RX
MAC
DMA
Engine
ECC
PB
ECC
TX Descr
Buffer
Parity
Flex
Filters
TX
MAC
Ethernet
CRC added
here
The specifics of the memory protection for each of the memories is shown in
Table 37-13, “Memory protection” on page 1419.
Table 37-13. Memory protection
Memory
Statistic
Registers
RX Filters
RX Flex Filters
Size
Protection Protection
Type
Bits
Description
64 x 32
ECC
128 x 32
Parity
128 x 36
Parity
8-bit ECC code is computed on 32-bit data
8
padded with 0s out to 64 bits for a total of 8
ECC bits (64x40)
4
parity computed on each byte for a total of 4
parity bits (128x36)
parity computed on each of 4 of the Filter
4
Value and on 4 bits of the Filter Mask for a
total of 5 parity bits (128x41)
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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