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EP80579 Datasheet, PDF (226/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line | |||
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Intel® EP80579 Integrated Processor
7.4.2
Gigabit Ethernet MAC: Bus M, Devices 0, 1, and 2, Function 0
The Gigabit Ethernet MAC includes the registers listed in Table 7-47 through
Table 7-44. These registers materialize in PCI configuration, I/O (via PCI BAR), and
memory (via PCI BAR) spaces. See Section 35.6, âGigabit Ethernet MAC Configuration
Spaces: Bus M, Device 0-2, Function 0â, Section 35.7, âGigabit Ethernet MAC I/O
Spaces: Bus M, Device 0-2, Function 0â, and Section 37.6, âGbE Controller Register
Summaryâ for detailed discussion of these registers along with alternative
materializations.
Table 7-47. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
09h
0Eh
10h
14h
2Ch
2Eh
34h
3Ch
3Dh
DCh
DDh
DEh
E0h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
F1h
F2h
01h
03h
05h
07h
08h
0Bh
0Eh
13h
17h
2Dh
2Fh
34h
3Ch
3Dh
DCh
DDh
DFh
E1h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
F1h
F3h
âOffset 00h: VID: Vendor Identification Registerâ on page 1241
8086h
âOffset 02h: DID: Device Identification Registerâ on page 1241
5040h
âOffset 04h: PCICMD: Device Command Registerâ on page 1243
0000h
âOffset 06h: PCISTS: PCI Device Status Registerâ on page 1244
10h
âOffset 08h: RID: Revision ID Registerâ on page 1245
Variable
âOffset 09h: CC: Class Code Registerâ on page 1245
020000h
âOffset 0Eh: HDR: Header Type Registerâ on page 1246
00h
âOffset 10h: CSRBAR: Control and Status Registers Base Address Registerâ on
page 1246
00000000h
âOffset 14h: IOBAR: CSR I/O Mapped BAR Registerâ on page 1247
00000001h
âOffset 2Ch: SVID: Subsystem Vendor ID Registerâ on page 1248
0000h
âOffset 2Eh: SID: Subsystem ID Registerâ on page 1248
0000h
âOffset 34h: CP: Capabilities Pointer Registerâ on page 1249
DCh
âOffset 3Ch: IRQL: Interrupt Line Registerâ on page 1249
00h
âOffset 3Dh: IRQP: Interrupt Pin Registerâ on page 1250
01h
âOffset DCh: PCID: Power Management Capability ID Registerâ on page 1251
01h
âOffset DDh: PCP: Power Management Next Capability Pointer Registerâ on
page 1251
E4h
âOffset DEh: PMCAP: Power Management Capability Registerâ on page 1252
X023h
âOffset E0h: PMCS: Power Management Control and Status Registerâ on
page 1253
0000h
âOffset E4h: SCID: Signal Target Capability ID Registerâ on page 1254
09h
âOffset E5h: SCP: Signal Target Next Capability Pointer Registerâ on page 1254 F0h
âOffset E6h: SBC: Signal Target Byte Count Registerâ on page 1255
09h
âOffset E7h: STYP: Signal Target Capability Type Registerâ on page 1255
01h
âOffset E8h: SMIA: Signal Target IA Mask Registerâ on page 1256
0h
âOffset ECh: SINT: Signal Target Raw Interrupt Registerâ on page 1257
00h
âOffset F0h: MCID: Message Signalled Interrupt Capability ID Registerâ on
page 1258
05h
âOffset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Registerâ on
page 1258
00h
âOffset F2h: MCTL: Message Signalled Interrupt Control Registerâ on page 1259 0000h
Intel® EP80579 Integrated Processor Product Line Datasheet
226
August 2009
Order Number: 320066-003US
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