EP80579 Datasheet, PDF (426/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 3 of 7)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 78h
Offset End: 7Bh
Size: 32 bit
Default: 242AD280h
Power Well: Core
Bit Range
22 :20
Bit Acronym
Bit Description
Sticky
Trrd
Row Delay: The required row delay period between two
activate commands accessing the same cs of a DIMM in
tCK cycles.
JEDEC recommendation for this parameter is based on the
device width. x8 devices = 7.5ns
Encoding
Number of CMDCLK
delays
000
No delay
001
1
010
2
N
011
3
100
4
101
5
110
6
111
7
Bit Reset
Value
010b
Bit Access
RW
Write Recovery Delay: The required write recovery delay
before being able to issue a precharge to the same page
accessing the same cs/bank of a DIMM in tCK cycles.
JEDEC recommendation for this parameter is 15ns min.
19 :17
Twr
Encoding
000
001
010
011
100
101
110
111
Number of CMDCLK
delays
2
3
4
5
6
7
8
9
N
101b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
426
August 2009
Order Number: 320066-003US