EP80579 Datasheet, PDF (1010/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-41. Offset 24h: USB2STS - USB 2.0 Status Register (Sheet 2 of 3)
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 24h
Offset End: 27h
Size: 32 bit
Default: 00001000h
Power Well: Core
Bit Range
04
03
02
Bit Acronym
Bit Description
Sticky
HS_ERR
FLRO
PCD
Host System Error:
0 = No serious error occurred during a host system
access involving the Host Controller module.
1 = The Host Controller sets this bit to 1 when a serious
error occurs during a host system access involving
the Host Controller module. Memory read cycles
initiated by the EHC that receive any status other
than Successful will result in this bit being set.
When this error occurs, the Host Controller clears the Run/
Stop bit in the Command register to prevent further
execution of the scheduled TDs. A hardware interrupt is
generated to the system (if enabled in the Interrupt
Enable Register).
Frame List Rollover:
0 = No Frame List Index rollover from its maximum value
to 0.
1 = The Host Controller sets this bit to a one when the
Frame List Index rolls over from its maximum value
to zero. Since only 1024-entry Frame List Size is
supported, the Frame List Index rolls over every time
FRNUM[13] toggles.
Port Change Detect: The Host Controller sets this bit to
a one when any port for which the Port Owner bit is set to
zero has a change bit transition from a zero to a one or a
Force Port Resume bit transition from a zero to a one as a
result of a J-K transition detected on a suspended port.
This bit will also be set as a result of the Connect Status
Change being set to a one after system software has
relinquished ownership of a connected port by writing a
zero to a port’s Port Owner bit.
This bit is allowed to be maintained in the Auxiliary power
well. Alternatively, it is also acceptable that, on a D3 to D0
transition of the EHCI HC device, this bit is loaded with the
OR of all of the PORTSC change bits (including Force port
resume, overcurrent change, enable/disable change and
connect status change). Regardless of the
implementation, whenever this bit is readable, i.e., in the
D0 state, it must provide a valid view of the Port Status
registers.
Bit Reset
Value
0h
0h
0h
Bit Access
RWC
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1010
August 2009
Order Number: 320066-003US