EP80579 Datasheet, PDF (704/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
17.1.5.5 Offset 31FFh: OIC - Other Interrupt Control Register
Table 17-24. Offset 31FFh: OIC - Other Interrupt Control Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 31FFh
Offset End: 31FFh
Size: 8 bit
Default: 0h
Power Well: Core
Bit Range
07 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
CEN
AEN
Reserved
Coprocessor Error Enable:
0 = FERR# does not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the IICH generates IRQ13 internally
and holds it until an I/O port F0h write. It also drives
IGNNE# active.
APIC Enable:
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
17.1.6
17.1.6.1
General Configuration Registers
Offset 3400h: RC - RTC Configuration Register
Table 17-25. Offset 3400h: RC - RTC Configuration Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3400h
Offset End: 3403h
Size: 32 bit
Default: 0h
Power Well: Core
Bit Range
31 : 05
04
Bit Acronym
Bit Description
Sticky
Reserved
UL
Reserved
Upper 128 Byte Lock:
0 = Bytes 38h-3Fh in the upper 128-byte bank of RTC
RAM are not locked and can be accessed. Writes are
not dropped and reads return any guaranteed data.
1 = Bytes 38h-3Fh in the upper 128-byte bank of RTC
RAM are locked and cannot be accessed. Writes are
dropped and reads do not return any guaranteed
data. Bit reset on system reset.
Bit Reset
Value
0h
0h
Bit Access
RO
RWO
Intel^® EP80579 Integrated Processor Product Line Datasheet
704
August 2009
Order Number: 320066-003US