EP80579 Datasheet, PDF (1680/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
42.4.1.4
must have a minimum value of one additional cycle (T3 >= 0x1). Programming the T3
– Strobe Timing parameter to be two clock cycles in length ensures that any data sent
to the DSP is captured regardless of when the EX_RDY signal is asserted by the DSP.
The Hold Phase of an Expansion-bus access is provided to allow a hold time for data to
remain valid after the data strobe has transitioned to an invalid state. During a write
access, the Hold Phase provides hold time for data written to an external device on the
Expansion bus, after the strobe pulse has completed.
During a read access, the Hold Phase allows an external device time to release the bus
after driving data back to the controller. The Hold Phase may be extended one to three
clock cycles, using bits 21:20 of the Timing and Control (EXP_TIMING_CS) Register, T4
– Hold Timing parameter. In HPI mode of operation, the Hold Phase is defined the same
as described for the Intel and Motorola modes of operation, but must be set to a
minimum value of one additional cycle (T4 >= 0x1).
After the address and chip select is de-asserted, the Expansion bus controller can be
programmed to wait a number of clocks before starting the next Expansion Bus access.
This action is referred to as the Recovery Phase. The Recovery Phase is may be
extended one to 15 clock cycles using bits 19:16 of the Timing and Control
(EXP_TIMING_CS) Register, T5 – Recovery Timing parameter. In HPI mode of
operation, the Recovery Phase is defined the same as described for the Intel and
Motorola modes of operation.
Using I/O Wait
The EX_IOWAIT_N signal is available to be shared by devices attached to chip selects 0
through chip select 7, when configured in Intel or Motorola modes of operation. The
shared device will assert EX_IOWAIT_N in the T2 phase of a read or write transaction.
During idle cycles, the board is responsible for ensuring that EX_IOWAIT_N is pulled-
up. Additionally, EX_IOWAIT_N must always be pulled high during Micron ZBT, Intel
Synchronous Mode, and HPI cycles. The Expansion bus controller will ignore
EX_IOWAIT_N for Synchronous Intel mode transfers and use the
EXP_SYNCINTEL_COUNT register for the wait state generation.
When an external device asserts EX_IOWAIT_N before the first cycle of a Strobe phase
of a read or write transaction, the Expansion bus controller will hold in the Strobe phase
until the EX_IOWAIT_N signal returns to an inactive state. Since there is a synchronizer
cell on EX_IOWAIT_N, the external device must assert EX_IOWAIT_N three cycles
before the deassertion of EX_WR_N/EX_RD_N. This implies that the value programmed
in the T2 and T3 phase cannot both be equal to zero. After EX_IOWAIT_N is deasserted
the Expansion bus controller will only transition to the T4 - Hold state after the T3
counter reaches zero.
Operation of EX_RDY signals is the same as the EX_IOWAIT_N signal, but is defined
primarily for the ‘C54xx family of DSPs. In addition, the EX_RDY signals will hold the
current access in the Address Phase if detected during that phase. This event can
happen if a busy DSP memory access is started before the previous access completes.
Figure 42-5 shows the operation of the EX_IOWAIT_N signal.
Notice that the access is an Intel Style Simplex Read access. The data strobe phase is
set to a value to last three clock cycles. The data is returned from the peripheral device
prior to the three clocks and the peripheral device de-asserts EX_IOWAIT_N. The data
strobe phase terminates after two clocks even though the strobe phase was configured
to pulse for three clocks.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1680
August 2009
Order Number: 320066-003US