EP80579 Datasheet, PDF (1473/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.3.13 IMC2 – Error Interrupt Mask Clear Register
Software uses this register to disable an interrupt condition that was previously
enabled. Interrupts are presented to the bus interface only when the mask bit is set
and the interrupt condition is active. The status of the mask bit is reflected in the “IMS0
– Interrupt 0 Mask Set/Read Register” on page 1459, and the status of the cause bit is
reflected in the “ICR0 – Interrupt 0 Cause Read Register” on page 1454. Software
disables a given interrupt by writing a 1 to the corresponding bit in this register, a 0 is
ignored.
Table 37-49. IMC2: Error Interrupt Mask Clear Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 08F8h
Offset End: 08FBh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 08F8h
Offset End: 08FBh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 08F8h
Offset End: 08FBh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 29
28
27
26
25 : 24
23
22
21
20
19 : 00
Bit Acronym
Bit Description
Sticky
Rsvd
Reserved
ERR_INTBUS Clears the mask for Internal Bus Error
ERR_STAT Clears the mask for Statistic Register ECC Error
ERR_INT Clears the mask for Internal Memory Error
Rsvd
Reserved
ERR_PKBUF Clears the mask for DMA Packet Buffer ECC Error
Rsvd
Reserved
ERR_TXDS
Clears the mask for DMA Transmit Descriptor Buffer ECC
Error
ERR_RXDS
Clears the mask for DMA Receive Descriptor Buffer ECC
Error
Rsvd
Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
WO
WO
WO
RV
WO
RV
WO
WO
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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