EP80579 Datasheet, PDF (1296/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 35-99. Offset 10h: CSRBAR: Control and Status Registers Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:6:0
Offset Start: 10h
Offset End: 13h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 12
11 : 04
03
02 : 01
00
Bit Acronym
Bit Description
Sticky
ADDR
ZERO
PREF
TYP
MEM
Upper Programmable Base Address: These bits are set
by BIOS to locate the base address of the region.
Lower Bits: Hardwired to 0 to set the region size to 4KB.
Prefetchable: Hardwired to 0 to indicate that the region is
not prefetchable.
Addressing Type: Hardwired to 0 to indicate a 32-bit
region.
Memory Space Indicator: Hardwired to 0 to identify the
region as in memory space.
Bit Reset
Value
0h
0h
0h
00b
0h
Bit Access
RW
RO
RO
RO
RO
35.10.1.9 Offset 2Ch: SVID – Subsystem Vendor ID Register
This register is a write-once register. Once any byte in the register has been written,
the register locks against further writes until reset.
Table 35-100.Offset 2Ch: SVID: Subsystem Vendor ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:6:0
Offset Start: 2Ch
Offset End: 2Dh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
SVID
Subsystem Vendor ID: This field must be programmed
during BIOS initialization.
Bit Reset
Value
0h
Bit Access
RWO
35.10.1.10 Offset 2Eh: SID – Subsystem ID Register
This register is a write-once register. Once any byte in the register has been written,
the register locks against further writes until reset,
Intel^® EP80579 Integrated Processor Product Line Datasheet
1296
August 2009
Order Number: 320066-003US