EP80579 Datasheet, PDF (7/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
9.4.2 Integrated Memory Init/Test Engine ......................................................... 258
9.4.3 Coherent Memory Write Buffer ................................................................. 258
9.4.4 RASUM Features .................................................................................... 258
9.4.4.1
9.4.4.2
SEC-DED ECC................................................................................. 259
Integrated Memory Scrub Engine ...................................................... 259
9.5 IMCH Feature List........................................................................................... 259
9.5.1 Memory Interface................................................................................... 259
9.5.2 PCI Express Interface in IMCH ................................................................. 259
9.5.3 EDMA Controller..................................................................................... 261
9.5.4 Coherent Memory Write Buffer ................................................................. 262
9.5.5 Integrated Memory Scrub Engine ............................................................. 262
9.5.6 Hardware Memory Initialization Engine...................................................... 262
9.5.7 System Management Functions ................................................................ 263
9.5.8 RASUM ................................................................................................. 263
9.6 IICH Feature List............................................................................................. 264
9.6.1 Low-Pin count (LPC) Interface and Firmware Hub (FWH) Interface ................ 264
9.6.2 Serial Peripheral Interface (SPI) ............................................................... 264
9.6.3 Integrated Serial ATA Host Controllers ...................................................... 264
9.6.4 USB .................................................................................................... 264
9.6.5 Interrupt Controller ................................................................................ 264
9.6.6 Power Management Logic ....................................................................... 265
9.6.7 DMA Controller ...................................................................................... 265
9.6.8 Timers Based on 82C54 .......................................................................... 265
9.6.9 High Precision Event Timers (HPET) .......................................................... 265
9.6.10 Real-Time Clock with 256-byte Battery-backed CMOS RAM .......................... 265
9.6.11 System TCO Reduction Circuits ............................................................... 265
9.6.12 SMBus .................................................................................................. 265
9.6.13 Watchdog Timer..................................................................................... 266
9.6.14 Serial Port............................................................................................. 266
9.6.15 GPIO .................................................................................................... 266
10.0 System Address Map ............................................................................................. 267
10.1 Overview ....................................................................................................... 267
10.1.1 System Memory Spaces .......................................................................... 268
10.1.2 VGA and MDA Memory Spaces ................................................................. 268
10.1.3 PAM Memory Spaces............................................................................... 270
10.1.4 TSEG SMM Memory Space ....................................................................... 274
10.1.5 PCI Express Enhanced Configuration Aperture ............................................ 274
10.1.6 IOAPIC Memory Space ............................................................................ 275
10.1.7 FSB Interrupt Memory Space ................................................................... 275
10.1.8 High SMM Memory Space ........................................................................ 276
10.1.9 PCI Device Memory (MMIO) ..................................................................... 276
10.1.9.1
10.1.9.2
10.1.9.3
Device 2 Memory and Prefetchable Memory........................................ 277
Device 3 Memory and Prefetchable Memory........................................ 277
Device 4 Memory and Prefetchable Memory........................................ 277
10.2 IMCH Responses to EDMA Transactions .............................................................. 278
10.2.1 Fixed Address Spaces (EDMA).................................................................. 278
10.2.2 Relocatable Address Spaces (EDMA) ......................................................... 278
10.3 I/O Address Space........................................................................................... 279
10.3.1 Configuration Window ............................................................................. 279
10.3.2 VGA and MDA Regions ............................................................................ 280
10.4 Main Memory Addressing.................................................................................. 281
10.5 System Management Mode (SMM) Space............................................................ 281
10.5.1 SMM Addressing Ranges ......................................................................... 281
10.5.1.1 SMM Space Restrictions ................................................................... 281
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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