EP80579 Datasheet, PDF (480/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.33 Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR
Command Register
This register enables various errors to generate a MCERR signal on the FSB. When an
error flag is set in the FERR or NERR registers, it generates a MCERR when enabled in
the MCERRCMD register.
Table 16-87. Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 7Eh
Offset End: 7Eh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 04
03
02
01
00
Reserved Reserved
Internal DRAM II/F to PMWB Parity Error MCERR
Enable: Generate MCERR when parity error detected for
DPMWB_MCER _{DRAM I/F to PMWB when this bit is set.}
R
0 = Disable
1 = Enable
Internal System Bus or I/O to PMWB Parity Error
MCERR Enable: Generate MCERR when parity error
IOPMWB_MCER _{detected on write port 0 when this bit is set.}
R
0 = Disable
1 = Enable
Internal PMWB to System Bus Parity Error MCERR
Enable: Generate MCERR when parity error detected for
PMWBSYS_MCE _{PMWB to System Bus when this bit is set.}
RR
0 = Disable
1 = Enable
Internal PMWB to DRAM I/F Parity Error MCERR
Enable: Generate MCERR when parity error detected for
PMWBD_MCER _{PMWB to DRAM I/F when this bit is set.}
R
0 = Disable
1 = Enable
Bit Reset
Value
00h
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
480
August 2009
Order Number: 320066-003US