EP80579 Datasheet, PDF (132/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
4.1.1
4.2
The IA complex attaches to the AIOC through a transparent PCI-to-PCI Bridge. Within
the AIOC, the “Signal Bridge” block in Figure 4-1 represents the hardware in the AIOC,
that converts signaling between the AIOC and IA domains and presents the appropriate
abstractions to agents on either side of the bridge.
Terminology and Conventions
Throughout this section, we use the following terminology:
• Global visibility: An operation is said to be globally visible when all side-effects of
the operation are visible to every observer in the system. For example, a write to
some resource (e.g., memory location, control register, etc.) R achieves global
visibility when a read of R by all other agents is guaranteed to return the new
value.
• Ordering: Ordering refers to the order in which signals and/or memory accesses to
different locations must reach global visibility to ensure some behavior. Note that
this excludes the “ordering” necessary to prevent data hazards which are accesses
to the same location.
• Signal: A message sent between agents to indicate some condition of interest. A
signal may be an interrupt, a memory write, etc. This section uses the term when
the specific transport medium is not important.
Existing Signaling Capabilities
There are several agents in the EP80579 that can be both the source and the target of
a “signal”: the IA-32 core and accelerators in the AIOC. In addition, there are several
other agents in the EP80579 that can be the source of a signal: devices in the IMCH or
IICH, the error reporting hardware, the Gigabit Ethernet MAC, the SSP interface, the
CAN interfaces, the IEEE 1588 interface, externally-attached PCI-Express devices, and
externally-attached local expansion bus devices (via GPIO or INTx interrupts). This
section summarizes the existing signaling capabilities of each of these agents.
When discussing signaling, this section classifies all signals into one of two general
categories:
• Ordered signals must maintain a particular relationship with the data stream. For
example, a MAC signals a CPU with an ordered signal after the MAC finishes writing
inbound packet data to memory.
• Unordered signals need not maintain a particular relationship with the data stream.
For example, memory interface hardware signals a CPU with an unordered signal
when the interface encounters an uncorrectable memory error.
Signals of either type may participate in producer/consumer operations between
agents; however, the operation can use only ordered signals if the producer/consumer
operation involves the data stream¹. Finally, note that this classification refers
specifically to the data stream; signals may also be ordered with respect to other
events (e.g., data being available in a local device buffer).
1. For producer/consumer operation to work correctly, software and hardware must be able to establish ordering relationships
between various events in the operation. Such a relationship cannot be established between the data stream and a signal that
is unordered with respect to the data stream.
Intel^® EP80579 Integrated Processor Product Line Datasheet
132
August 2009
Order Number: 320066-003US