EP80579 Datasheet, PDF (553/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-178.Offset 5Ah: MSICAPA - MSI Capabilities Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 5Ah
Offset End: 5Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 5Ah
Offset End: 5Bh
Size: 16 bit
Default: 0002h
Power Well: Core
Bit Range
15 : 08
07
06 : 04
03 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
64AC
MME
MMC
MSIE
Reserved
Indicates 64-bit Address Capable: Hardwired to ‘0’ to
indicate that the PCI Express* bridge is capable of 32-bit
MSI addressing.
Multiple Message Enable: The software writes this field
to indicate the number of allocated messages, which is
aligned to a power of two. When MSI is enabled, the
software allocates at least one message to the device.
Multiple Message Capable: The PCI Express* requests a
capability for two messages by initializing this field to a
value of 001b.
MSI Enable: Software sets this bit to select the method of
interrupt delivery. If no interrupts are enabled, software
must poll for status since no interrupts of either type are
generated.
0 = Legacy interrupts are generated.
1 = Message Signaled Interrupts (MSI) are generated.
Bit Reset
Value
00h
0b
0h
001b
0b
Bit Access
RO
RW
RO
RW
16.4.1.40 Offset 5Ch: MSIAR - MSI Address for PCI Express* Register
The MSI Address Register (MSIAR) contains all the address related information to route
MSI interrupts.
Table 16-179.Offset 5Ch: MSIAR - MSI Address for PCI Express Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 5Ch
Offset End: 5Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 5Ch
Offset End: 5Fh
Size: 32 bit
Default: FEE00000h
Power Well: Core
Bit Range
31 : 20
19 : 12
11 : 04
Bit Acronym
Bit Description
Sticky
MSIA
Address: Most significant 12 bits of 32-bit address.
Destination ID: Should reflect the 63:56 bits of IOxAPIC
DESID
redirection table entry. The IMCH may substitute other
Y
values in this field when redirecting to the System Bus.
EXDID
Extended Destination ID: Should reflect the 55:48 bits
of IOxAPIC redirection table entry.
Bit Reset
Value
FEEh
00h
00h
Bit Access
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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