EP80579 Datasheet, PDF (828/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.1.16 Offset 3Ch: INTR - Interrupt Information Register
Table 23-19. Offset 3Ch: INTR - Interrupt Information Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 3Ch
Offset End: 3Dh
Size: 16 bit
Default: Variable
Power Well: Core
Bit Range
15 : 08
07 : 00
Bit Acronym
Bit Description
Sticky
IPIN
ILINE
Interrupt Pin (IPIN): This reflects the value of
D31IP.SIP in chipset configuration space.
Interrupt Line (ILINE): Software written value to
indicate which interrupt line (vector) the interrupt is
connected to. No hardware action is taken on this register.
Bit Reset
Value
Variable
00h
Bit Access
RO
RW
23.1.2
Warning:
Note:
Additional SFF-8038i Configuration Registers
The following registers are necessary to implement as read/write bits in order to
maintain software functionality for the SFF-8038i mode of operation (a.k.a. Bus Master
IDE). They have no bearing on Serial ATA operation unless otherwise indicated, but are
necessary to be read/write for legacy software capability.
The default values are defined with an h for hex, a bi for binary, or 00 for zero. If there
is not a letter following the default value, assume it is a binary number.
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
Reserved bits are Read Only.
Start
40
42
44
48
4A
54
End
41
43
44
48
4B
57
Symbol
PTIM
STIM
D1TIM
SYNCC
SYNCTIM
IIOC
Name
Primary IDE Timing
Secondary IDE Timing
Slave IDE Timing
Synchronous DMA Control Register
Synchronous DMA Timing Register
IDE I/O Configuration
Intel^® EP80579 Integrated Processor Product Line Datasheet
828
August 2009
Order Number: 320066-003US