EP80579 Datasheet, PDF (301/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Please refer the Section 16.1.1.49, “Offset B0h: DDR2ODTC - DDR2 ODT Control
Register” for more details on the CSR that needs to be programmed by BIOS so that
the memory controller drives the proper ODT control signals.
Note:
The memory controller will not enable ODT before the write command is issued on the
DRAM interface (See Table 11-15 for more details). For configurations with CL=3,
WL=2 the controller will assert the ODT pin along with the write command. This will
result in the termination in the inactive slot to be enabled at the same time the
controller starts driving the DQ data bus.
Figure 11-5. ODT Timing on Back-to-Back Writes to Different Slots
0
1
2
3
4
5
6
7
8
Write A
Slot 1
ODT
Slot 2
ODT
Slot 1
Write A
Slot 2
DQ
Slot 2
Rtt
WL = 3
tOND = 2 tCK
Slot 1
Rtt
WL = 3
BL = 4
Termination ON Slot 2
tONF = 2.5 tCK
tOND = 2 tCK
BL = 4
Termination ON Slot 1
tONF = 2.5 tCK
11.4.3
On-Die Termination (ODTZ) on the EP80579
The EP80579 supports ODT (referred to as ODTZ to differentiate it from the On-
DIMMDie Termination, ODT that is implementation on the DRAM devices) on the DQ/
DQS buffers to improve signal integrity on the inbound path (read data from DRAM).
ODTZ will be enabled on read accesses to the DRAM devices and can be in one of the 3
states - 60ohms, 120ohms or off. ODTZ will be automatically disabled when the
EP80579 DQ/DQS buffers are enabled for a write access to the DRAM device. There are
no timing parameters implemented to control this functionality and the DDRIO pads are
responsible for ensuring that ODTZ is in the disabled state when issuing writes to the
DRAM devices.
The termination value for ODTZ can be set by programming the ODTZENA bit in Section
16.1.1.45, “Offset 88h: SDRC – DDR SDRAM Secondary Control Register”.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
301