EP80579 Datasheet, PDF (1717/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
45.0 IMCH Design for Test
45.1
IMCH Design for Test Features
45.1.1
Features
The IMCH includes a number of Design For Test features. These features are described
this section.
45.2
JTAG
45.2.1
IMCH JTAG Instructions
Table 45-1 below lists the JTAG chains, their public or private designation, the chain
length, and a short descriptive name. The chains are described in more detail in later
sections.
Due to the nature of the JTAG design in EP80579, there are two operating modes in
which the instructions below are accessible. In the default serial mode (i.e. MCH JTAG
+ IA-32 core JTAG), the TDI value represents the full input instruction required.
Table 45-1. IMCH JTAG Instructions
Mnemonic
ExTest
SampPre
IDCode
HighZ
ByPass
Parallel
Mode IR
00000000
00000001
00000010
00001000
11111111
Hex
Serial Mode IR
00 000000001111111
01 000000011111111
02 000000101111111
08 000010001111111
FF 111111111111111
Hex
007F
00FF
017F
047F
7FFF
Public
Chain
Length
Description
Public
884
Public
884
Public
32
Public
0
Public
0
Extest
Sample Preload
IDCode
HighZ
Bypass
45.2.1.1
JTAG Chain Details
Descriptions follow for the JTAG chain.
45.2.1.1.1 ExTest
The ExTest instruction allows circuitry or wiring external to the devices to be tested.
Output boundary scan register cells are used to apply stimulus, while boundary scan
cells at the inputs pins are used to capture data. I/O cells can be used for either
purpose, depending on the value set in the corresponding output enable cell.
Note that some signals are prevented from driving out during ExTest: xxpwrgd,
xxrstinn, and xxextintrnn.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1717