EP80579 Datasheet, PDF (1702/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
42.5.2 Configuration and Status Registers
42.5.2.1
EXP_CNFG0 - Configuration Register 0
At power up or whenever RESET_IN_N is asserted, the Expansion-bus address outputs
are switched to inputs and the states of the bits are captured and stored in
Configuration Register 0. This occurs when RESET_OUT_N is deasserted.
Only bits EX_ADDR[23:21] are used.
These configuration bits are made available to the system as outputs from the
Expansion bus controller block. The bits are read-only.
Table 42-8. EXP_CNFG0 -Configuration Register 0
Description: Defines the reset-time configuration straps.
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:8:0
Offset Start: 00000020h
Offset End: 00000020h
Size: 32 bit
Default: 00000040h
Power Well: Core
Bit Range
31 :24
23 :21
20 :11
10
Bit Acronym
Bit Description
Sticky
RSVD
LEB_SIZE
RSVD
EXIOW
Reserved
These bits are initialized from EX_ADDR[23:21] at reset
using the reset-time strapping mechanism described
above. This field always contains the value read from the
straps at reset and is not updated in the event BIOS over-
rides the value of LEB_SIZE.
The effect of these bits is defined in Table 35-159,
“MMBAR ADDR Field Behavior” on page 1325
Reserved
1 = EX_IOWAIT_N is sampled during the read/write
Expansion bus cycles as defined in Section 42.4.1.4,
“Using I/O Wait” on page 1680 for Chip Select 0.
0 = EX_IOWAIT_N is ignored for read and write cycles to
Chip select 0 if EXP_TIMING_CS0 is configured to Intel
mode. Typically, IOWAIT_CS0 must be pulled down to Vss
when attaching a Synchronous Intel StrataFlash on Chip
select 0 since the default mode for EXP_TIMING_CS0 is
Intel mode and EX_IOWAIT_N is an unknown value for
Synchronous Intel StrataFlash. If the board does not
connect the Synchronous Intel StrataFlash WAIT pin to
EX_WAIT_N (and the board guarantees EX_IOWAIT_N is
pulled up), the value of IOWAIT_CS0 is a don’t care since
EX_IOWAIT_N will not be asserted. When
EXP_TIMING_CS0 is reconfigured to Intel Synchronous
mode during boot-up (for Synchronous Intel chips), the
Expansion bus controller ignores EX_IOWAIT_N during
read and write cycles since the WAIT functionality is
determined from the EXP_SYNCINTEL_COUNT and
EXP_TIMING_CS registers.
Bit Reset
Value
0h
X
0h
0h
Bit Access
RO
RO
RO
RO
9 :7
6
5
4
3 :0
RSVD
RSVD
RSVD
RSVD
RSVD
Reserved
Reserved
Reserved
Reserved
Reserved
0h
RO
1h
RO
0h
RO
0h
RW
0h
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1702
August 2009
Order Number: 320066-003US