EP80579 Datasheet, PDF (1236/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 35-2. Messaging and Signalling Capability Record per PCI Device (Sheet 2 of 2)
PCI
Device
3
(MDIO)
4
(CAN 0)
5
(CAN 1)
6
(SSP)
7
(1588)
8
(Local
Expansion
Bus)
Function
MDIO
CAN
CAN
SSP
1588
Interface
Local
Expansion
Bus
Message
Capable?
No
Yes
Yes
Yes
Yes
Yes
Signal
Capable?
Interrupts
(Max 8 per device)
No
CAN0 System Interrupt
Yes
CAN0 Parity Interrupt
CAN1 System Interrupt
Yes
CAN1 Parity Interrupt
Yes
SSP Interrupt
Yes
IEEE 1588 Interrupt
EXP Expansion-Bus Parity Error
Yes
Internal Interrupt
Comment
35.5
Power Management of AIOC Devices
The AIOC devices support PCI Bus power management (PM). The supported states are:
• D0: Device is on and running which maximum power dissipation
• D3: Device is off and power can be removed. The device has lost its context
information and will have be re-booted before it can enter the D0 state again.
The PM capabilities for the AIOC devices are defined as part of the capabilities list in the
PCI Configuration space for each device. Figure 35-3 describes the contents of a power
management entry in the capability list.
Figure 35-3. PCI Power Management Register Block
Byte 3
Byte 2
Power Management Capabilities
(PMC)
Data
PMCSR_BSE
Bridge Support
Extensions
Byte 1
Byte 0
Next Item Ptr Capability ID
Power Management Control /
Status Register (PMCSR)
Note:
PMCSR control bits are provided in part of PCI PM registers. These bits control the state
of the device. The default value of this bit is 0 and corresponds to the D0 state.
It is the responsibility of software to ensure that the devices and all of its function are
in quiescent state
It is also the responsibility of software to disable Memory, I/O space (as appropriate)
disabled, and interrupts (as appropriate) in the PCICMD register prior to powering
down the device.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1236
August 2009
Order Number: 320066-003US