EP80579 Datasheet, PDF (607/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-230.Interpretation of DCALADDR (Sheet 2 of 2)based on DCALCSR.OPCODE
NOP, Refresh, Pre-Charge,
MRS/EMRS, and Self-Refresh
Bit
Entry Commands initiated by
DCALCSR
Receive Enable
DQS Delay Cal
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
16.5.1.5
Column Address 15 to 11 & 9 to 2
Column Address 15 to 11 & 9 to 2
DRAM Bank Address Bus 2:0
Bank Address 2:0
Bank Address 2:0 in
DCALCSR.BASPAT=1 mode, not used
in DCALCSR.BASPAT=0 mode
Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Registers
Table 16-231.Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Register
Description: DCALData - DRAM Calibration Data Registers
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 48h at 1h
Offset End: 48h at 1h
Size: 8 bit
Default: 00000000h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
DCALDATA
DCAL Data and other information based on
DCALCSR.OPCODE. See Table 16-232.
Sticky
Bit Reset
Value
Bit Access
N
00h
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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