EP80579 Datasheet, PDF (825/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-13. Offset 18h: SCMDBA – Secondary Command Block Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 18h
Offset End: 1Bh
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 : 16
15 : 03
02 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
BAR
Reserved
RTE
Reserved
Base Address (BAR): Base address of the I/O space (8
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE): Indicates a request for
IO space
Bit Reset
Value
0h
0h
0h
1h
Bit Access
RO
RW
RO
RO
23.1.1.11 Offset 1Ch: SCTLBA – Secondary Control Block Base Address Register
This 4-byte I/O space is used in Native Mode for the Secondary Controller’s Control
Block.
Table 23-14. Offset 1Ch: SCTLBA – Secondary Control Block Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 1Ch
Offset End: 1Fh
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 : 16
15 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
BAR
Reserved
RTE
Reserved
Base Address (BAR): Base address of the I/O space (4
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE): Indicates a request for
IO space.
Bit Reset
Value
0h
0h
0h
1h
Bit Access
RO
RW
RO
RO
23.1.1.12 Offset 20h: LBAR – Legacy Bus Master Base Address Register
This BAR is used to allocate I/O space for the SFF-8038i mode of operation (aka Bus
Master IDE) and AHCI index/data pair.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
825