EP80579 Datasheet, PDF (1233/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.0 PCI-to-PCI Bridge: AIOC Configuration
35.1
Overview
The PCI-to-PCI bridge provides the IA-32 core/MCH fabric an interface to the AIOC. It
implements PCI configuration registers that enable the IA-32 core to enumerate and
configure the AIOC devices.
35.2
Feature List
The PCI-to-PCI bridge implements the following:
• Provides the IA-32 core/MCH complex access into the AIOC.
35.3
PCI Configuration Registers
The AIOC Type 1 PCI configuration registers can only be accessed using Type 1 Config
Read/Write request types.
35.3.1
Description of PCI Configuration Header Space
The PCI configuration headers expose the various PCI devices on the AIOC to the IA
infrastructure.
The PCI Specification requires implementation of 64 bytes of PCI Configuration
registers as shown in Table 35-1. After a system reset, these registers are initially
configured by the BIOS, and/or “Plug and Play” aware operating system. Device drivers
will then read these registers to determine what resources (interrupt number, memory
mapping location, etc.), the BIOS and/or OS assigned to the device.
Table 35-1. Type 0 PCI Configuration Header
Byte Offset
+7
+6
+5
+4
Status
Command
BIST
Type
LT
CLS
Base Address 1
Base Address 3
Base Address 5
Subsys ID
Subsys ID
Reserved
CP
Mx L
Mn G
IRQ P
IRQ L
+3
+2
+1
+0
Device ID
Vendor ID
Class Code
Rev
Base Address 0
Base Address 2
Base Address 4
CardBus CIS Pointer
Expansion ROM Base
Reserved
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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