EP80579 Datasheet, PDF (395/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.8 Offset 0Eh: HDR - Header Type Register
Table 16-9. Offset 0Eh: HDR - Header Type Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 0Eh
Offset End: 0Eh
Size: 8 bit
Default: 80h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
HDR
Note:
PCI Header: The header type of the IMCH Device
0.
80h = multi-function device with standard header
layout.
This register should return a 00h indicating a
single function device, when both functions 1 and
2 are disabled.
Bit Reset
Value
80h
Bit Access
RO
16.1.1.9
Note:
Offset 14h: SMRBASE - System Memory RCOMP Base Address Register
The SMRBASE is a standard PCI Base Address register that is used to set the base of
the Memory Mapped Registers used to control the System Memory I/O Buffer RCOMP.
In addition to calibration, the DCAL engine which resides within this memory mapped
region also performs RAS functions. In addition, there are some BIOS scratch registers
within this region. The actual behavior of this register depends on the SMRCOMP MMR
Enable bit in the IMCH TST2 register (Device 0, Function 0, Offset F6, Bit 6). When
IMCH TST2[6] is set, this register behaves like a standard PCI BAR requesting 4 Kbyte
of address space. When IMCH TST2[6] is clear, this register is hardwired to all zeros,
effectively disabling the BAR and the corresponding SM MMR region. Because of the
more extensive functionality supported by DCAL, it is expected that once this address
space has been enabled by System BIOS, it remains enabled to support various RAS
features.
All accesses to these Memory Mapped Registers must be made as a single Dword (4
bytes) or less. Access must be aligned on a natural boundary.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
395