EP80579 Datasheet, PDF (1447/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-29. EEPROM_CTRL - EEPROM Control Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0010h
Offset End: 0013h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0010h
Offset End: 0013h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0010h
Offset End: 0013h
Size: 32 bits
Default: 00000X1Xh
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
EE_DI
EE_CS
EE_SK
Data Input to the EEPROM.
When EE_GNT is 1, the EE_DI output signal is mapped
directly to this bit. Software provides data input to the
EEPROM via writes to this bit.
Chip Select Input to the EEPROM.
When EE_GNT is 1, the EE_CS output signal is mapped to
the chip select of the EEPROM device. Software enables the
EEPROM by writing a 1 to this bit.
Clock Input to the EEPROM.
When EE_GNT is 1, the EE_SK output signal is mapped to
this bit and provides the serial clock input to the EEPROM.
Software clocks the EEPROM via toggling this bit with
successive writes.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RW
This register provides software direct access to the EEPROM. Software can control the
EEPROM by successive writes to this register. Data & address information is clocked
into the EEPROM by software toggling the EESK bit (2) of this register with EECS set to
1. Data output from the EEPROM is latched into bit 3 of this register via the internal
62.5MHz clock and may be accessed by software via reads of this register.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1447