EP80579 Datasheet, PDF (1483/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-58. RDTR: RX Interrupt Delay Timer (Packet Timer) Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 2820h
Offset End: 2823h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 2820h
Offset End: 2823h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 2820h
Offset End: 2823h
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range
31
30 : 16
15 : 00
Bit Acronym
Bit Description
Sticky
FPD
Rsvd
RPDT
Flush Partial Descriptor. Writing this bit with 1 initiates
an immediate expiration of the timer, causing a writeback
of any consumed receive descriptors pending writeback,
and results in a receive timer interrupt in the ICR register.
This bit is self clearing and always reads 0.
Reserved
Receive Packet Delay Timer
Timer increments are
RMII: 1.28 microseconds
RGMII: 1.024 microseconds.
See register description above
Bit Reset
Value
0h
0h
0h
Bit Access
WO
RV
RW
37.6.4.10 RXDCTL – Receive Descriptor Control Register
This register controls the fetching and write-back of receive descriptors. The three
threshold values are used to determine when descriptors will be read from and written
to host memory. The values may be in units of cache lines or 16B descriptors.
Table 37-59. RXDCTL: Receive Descriptor Control Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 2828h
Offset End: 282Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 2828h
Offset End: 282Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 2828h
Offset End: 282Bh
Size: 32 bits
Default: 00010000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
31 : 25
Rsvd
Reserved
Bit Description
Sticky
Bit Reset
Value
0h
Bit Access
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1483