EP80579 Datasheet, PDF (899/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-6. Offset 06h: DS – Device Status Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0280h
Power Well: Resume
Bit Range
08
07
06
05
04
03
02 : 00
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
Reserved
Reserved
CAP_LIST
INTS
Reserved
Reserved
Reserved
Reserved
Reserved
Capabilities List Indicator: Hardwired to ‘0’ because
there are no capability list structures in this function
Interrupt Status: This bit indicates that an interrupt is
pending. It is independent from the state of the Interrupt
Enable bit in the command register.
Reserved
Bit Reset
Value
0h
1h
0h
0h
0h
0h
00h
Bit Access
RO
RO
24.2.1.5
Offset 08h: RID: Revision ID Register
The value reported in this register depends on the value written to the Revision ID in
Device 31, Function 0, Offset 08h. See Chapter 19.0, “LPC Interface: Bus 0, Device 31,
Function 0,” for details.
Table 24-7. Offset 08h: RID: Revision ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: Variable
Power Well: Resume
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Indicates the revision identifier. The value reported in this
register depends on the value written to the Revision ID in
RID
Device 31, Function 0, Offset 08h. This register follows the
ICH revision ID scheme as defined in Section 19.2.1.4,
“Offset 08h: RID - Revision ID Register” on page 736.
Bit Reset
Value
Variable
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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