EP80579 Datasheet, PDF (735/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.2.1.2 Offset 04h: CMD: Device Command Register
Table 19-3. Offset 04h: CMD: Device Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0007h
Power Well: Core
Bit Range
15 :10
09
08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
FBE
SEE
WCC
PERE
VGA_PSE
MWIE
SCE
BME
MSE
IOSE
Reserved
Fast Back to Back Enable: Hardwired to ‘0’ as per PCI
Express Specification.
SERR# Enable:
0 = LPC bridge does not generates SERR#
1 = LPC bridge generates SERR#
Wait Cycle Control: Hardwired to ‘0’ as per PCI Express
Specification.
Parity Error Response Enable:
0 = No action is taken when detecting a parity error.
1 = Enables the LPC bridge to respond to parity errors
detected on IICH interface.
VGA Palette Snoop: Hardwired to ‘0’ as per PCI Express
Specification.
Memory Write and Invalidate Enable: Hardwired to
‘0’as per PCI Express Specification.
Special Cycle Enable: Hardwired to ‘0’ as per PCI
Express Specification.
Bus Master Enable: Bus Masters cannot be disabled.
Memory Space Enable: Memory space cannot be
disabled on LPC.
I/O Space Enable: I/O space cannot be disabled on LPC.
Bit Reset
Value
00h
0h
0h
0h
0h
0h
0h
0h
1
1
1
Bit Access
RO
RW
RO
RW
RO
RO
RO
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
735