EP80579 Datasheet, PDF (1751/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
48.4.3.6 UART Interface
Table 48-16. UART Signals (Sheet 1 of 3)
Signal Name
SIU_CTS1#
SIU_CTS2#
SIU_DCD1#
SIU_DCD2#
SIU_DSR1#
IO Type
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
Direction
Ball
Count
I/O
1
I/O
1
I/O
1
I/O
1
I/O
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
UART Port 1 Clear to Send: Active low, this pin
indicates that data can be exchanged between
UART port 1 and the external interface. This pin
has no effect on the transmitter.
BSC
BSC
Note: This pin could be used as Modem Status
Input whose condition can be tested by the
processor by reading bit 4 (CTS) of the Modem
Status register (MSR). Bit 4 is the compliment of
the CTS# signal. Bit0 (DCTS) of the MSR
indicates whether the CTS# input has changed
state since the previous reading of the MSR.
When the CTS bit of the MSR changes state an
interrupt is generated if the Modem Status
Interrupt is enabled.
UART Port 2 Clear to Send. Refer to UART Port 1
Clear to Send (SIU_CTS1#) for more
information.
UART Port 1 Data Carrier Detect: Active low, this
pin indicates that data carrier has been detected
by the external agent for UART port 1.
BSC
BSC
Note: This pin is Modem Status Input which
condition can be tested by the processor by
reading bit 7 (DCD) of the Modem Status
Register (MSR). Bit 7 is complement of the
DCD# signal. Bit 3 (DDCD) of the MSR indicates
whether the DCD# input has changed state
since the previous reading of the MSR. When the
DCD bin of the MSR changes state an interrupt
is generated if the Modem Status Interrupt is
enabled.
UART Port 2 Data Carrier Detect. Refer to UART
Port 1 Data Carrier Detect (SIU_DCD1) for more
information.
UART Port 1 Data Set Ready: Active low, this pin
indicates that the external agent is ready to
communicate with UART port 1. This pin has no
effect on the transmitter.
BSC
Note: This pin could be used as Modem Status
Input whose condition can be tested by the
processor by reading bit 5 (DSR) of the Modem
status register (MSR). Bit 5 is the complement
of the DSR# signal. Bit 1 (DDSR) of the Modem
status register (MSR) indicates whether the
DSR# input has changed state since the
previous reading of the MSR. When the DSR bin
of the MSR changes state an interrupt is
generated if the Modem Status Interrupt is
enabled.
SIU_DSR2#
LVTTL,3.3V I/O
1
BSC
UART Port 2 Data Set Ready. Refer to UART Port
1 Data Set Ready for more information.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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