EP80579 Datasheet, PDF (372/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 15-1. SMBus Register Summary
Symbol
CMD
BYTCNT
ADDR3
ADDR2
ADDR1
ADDR0
DATA3
DATA2
DATA1
DATA0
STS
Full Name/Function
Command
Byte Count
Bus Number (Only lower five bits are utilized)
Device/Function Number
Extended Reg Number (Bits 03:00 - 4 k page extension)
Register Number (offset into function space)
Data, fourth byte (31:24)
Data, third byte (23:16)
Data, second byte (15:08)
Data, first byte (07:00)
Status, only for reads
Table 15-2. SMBus Memory-Mapped Register Summary
Symbol
CMD
BYTCNT
ADDR3
ADDR2
ADDR1
ADDR0
DATA3
DATA2
DATA1
DATA0
STS
Full Name/Function
Command
Byte Count
Destination Memory (BAR Selection)
Address Offset 23:16 (Filler-used to zero out register)
Address Offset 15:08 (15:12 not used)
Address Offset 07:00 (11:00 used for 4 K page)
Data, fourth byte (31:24)
Data, third byte (23:16)
Data, second byte (15:08)
Data, first byte (07:00)
Status, only for reads
Table 15-3. ADDR3 Memory Assignments
ADDR3
00_000000
00_000001
00_001000
All others
Destination Memory Assignments
NSI
EDMA
DDR2
Reserved
Table 15-1 and Table 15-2 indicate the sequence of data as it is presented on the
SMBus following the byte address of the IMCH itself. This is not necessarily to indicate
any specific register stack or array implemented in the IMCH. The registers can take on
different meanings depending on whether it is a configuration or memory-mapped
access type. The command indicates how to interpret the registers. Refer to the
System Management Bus (SMBus) Specification, Version 2 for interface protocol
details.
Intel^® EP80579 Integrated Processor Product Line Datasheet
372
August 2009
Order Number: 320066-003US