EP80579 Datasheet, PDF (15/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16.4.1.50 Offset 74h: PEALNKCTL - PCI Express* Link Control Register ................ 562
16.4.1.51 Offset 76h: PEALNKSTS - PCI Express* Link Status Register ................. 564
16.4.1.52 Offset 78h: PEASLTCAP - PCI Express* Slot Capabilities Register........... 565
16.4.1.53 Offset 78h: PEA1SLTCAP - PCI Express* Slot Capabilities Register......... 566
16.4.1.54 Offset 7Ch: PEASLTCTL - PCI Express* Slot Control Register ................ 568
16.4.1.55 Offset 7Eh: PEASLTSTS - PCI Express* Slot Status Register ................. 569
16.4.1.56 Offset 80h: PEARPCTL - PCI Express* Root Port Control Register........... 570
16.4.1.57 Offset 84h: PEARPSTS - PCI Express* Root Port Status Register............ 571
16.4.1.58 Offset 100h: ENHCAPST - Enhanced Capability Structure Register ......... 571
16.4.1.59 Offset 104h: UNCERRSTS - Uncorrectable Error Status Register ............ 572
16.4.1.60 Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register ............. 574
16.4.1.61 Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register ......... 575
16.4.1.62 Offset 110h: CORERRSTS - Correctable Error Status Register ............... 576
16.4.1.63 Offset 114h: CORERRMSK - Correctable Error Mask Register................. 578
16.4.1.64 Offset 118h: AERCACR - Advanced Error Capabilities and
Control Register.............................................................................. 579
16.4.1.65 Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register.......... 580
16.4.1.66 Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register ......... 580
16.4.1.67 Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register ......... 581
16.4.1.68 Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register.......... 581
16.4.1.69 Offset 12Ch: RPERRCMD - Root (Port) Error Command Register ............ 582
16.4.1.70 Offset 130h: RPERRMSTS - Root (Port) Error Message Status
Register ........................................................................................ 583
16.4.1.71 Offset 134h: ERRSID - Error Source ID Register.................................. 585
16.4.1.72 Offset 140h: PEAUNITERR - PCI Express* Unit Error Register................ 585
16.4.1.73 Offset 144h: PEAMASKERR - PCI Express* Unit Mask Error
Register ........................................................................................ 588
16.4.1.74 Offset 148h: PEAERRDOCMD - PCI Express* Error Do
Command Register ......................................................................... 589
16.4.1.75 Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask
Register ........................................................................................ 591
16.4.1.76 Offset 150h: COREDMASK - Correctable Error Detect Mask
Register ........................................................................................ 592
16.4.1.77 Offset 158h: PEAUNITEDMASK - PCI Express* Unit Error Detect Mask Register
594
16.4.1.78 Offset 160h: PEAFERR - PCI Express* First Error Register .................... 595
16.4.1.79 Offset 164h: PEANERR - PCI Express* Next Error Register.................... 597
16.4.1.80 Offset 168h: PEAERRINJCTL - Error Injection Control Register .............. 597
16.5 Memory Mapped I/O Registers for DRAM Controller.............................................. 599
16.5.1 Detailed Register Description ................................................................... 601
16.5.1.1 Offset 00h: NOTESPAD - Note (Sticky) Pad for BIOS Support
Register ........................................................................................ 601
16.5.1.2 Offset 02h: NOTEPAD - Note Pad for BIOS Support Register ................. 601
16.5.1.3 Offset 40h: DCALCSR – DDR Calibration Control and Status
Register ........................................................................................ 602
16.5.1.4 Offset 44h: DCALADDR - DDR Calibration Address Register .................. 606
16.5.1.5 Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Registers........... 607
16.5.1.6 Offset 94h: RCVENAC - Receiver Enable Algorithm Control
Register ........................................................................................ 611
16.5.1.7 Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control
611
16.5.1.8 Offset 9Ch: DQSFAIL1 - DQSFAIL1 Configuration Register .................... 612
16.5.1.9 Offset A0h: DQSFAIL0 - DQSFAIL0 Configuration Register .................... 613
16.5.1.10 DRRTC: Receive Enable Reference Output Timing Control Registers ....... 614
16.5.1.11 Offset A4h: DRRTC00 - Receive Enable Reference Output Timing Control
Register ........................................................................................ 615
16.5.1.12 Offset A8h: DRRTC01 - Receive Enable Reference Output Timing Control
Register ........................................................................................ 616
16.5.1.13 Offset C4h: DRRTC02 - Receive Enable Reference Output Timing Control
Register ........................................................................................ 616
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
15