EP80579 Datasheet, PDF (831/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-21. Offset 44h: D1TIM – Device 1 IDE Timing Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 44h
Offset End: 44h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
05 : 04
03 : 02
01 : 00
Bit Acronym
Bit Description
Sticky
SRCT1
PISP1
PRCT1
Secondary Device 1 Recovery Time (SRCT1):
Determines the minimum number of 33 MHz clocks
between the last IORDY sample point and the IOR#/IOW#
strobe of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
Primary Device 1 IORDY Sample Point (PISP1):
Same as bits 7:6, except for the primary device.
Primary Device 1 Recovery Time (PRCT1): Same as
bits 5:4, except for the primary device.
Bit Reset
Value
00h
00h
00h
Bit Access
RW
RW
RW
23.1.2.4 Offset 48h: SYNCC – Synchronous DMA Control Register
Table 23-22. Offset 48h: SYNCC – Synchronous DMA Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 48h
Offset End: 48h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
SDAE1
SDAE0
PDAE1
PDAE0
Reserved
Secondary Device 1 ATAxx Enable (SDAE1): When
set, enables ATA33/66/100/133 timing modes for the
secondary slave device.
Secondary Device 0 ATAxx Enable (SDAE0): When
set, enables ATA33/66/100/133 timing modes for the
secondary master device.
Primary Device 1 ATAxx Enable (PDAE1): When set,
enables ATA33/66/100/133 timing modes for the primary
slave device.
Primary Device 0 ATAxx Enable (PDAE0): When set,
enables ATA33/66/100/133 timing modes for the primary
master device.
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RO
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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