EP80579 Datasheet, PDF (154/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
5.5.1
Handling Out-of-Bounds Addresses
The memory controller does not perform any bounds checking on system addresses
that it receives from other agents. As a result, the behavior of the EP80579 in response
to an access to a DRAM location that is outside the range of populated memory
depends on the source of the transaction and the path it takes through the device.
There are two paths of relevance to this discussion: the Coherent path through the
IMCH and the AIOC-Direct path directly to the memory controller.
Accesses to locations above top of memory along the Coherent path (from either AIOC
agents via the AIOC-interface, the IA-32 core, or other agents attached to the CMI
through PCI Express*, etc.) will be aborted by the IMCH. The specific manner of the
abort depends on whether the transaction originates from the IA-32 core or a AIOC
agent.
Access to locations above top of memory along the AIOC-Direct path (from the AIOC
Memory Target) are not aborted or otherwise trapped by default. The results of such
transactions are undefined and may alias onto populated memory regions. As a result,
software must program the EP80579 so that it can never generate an AIOC-Direct
system address above TOM. The Memory Target provides the ability to log range errors
(and optionally halt the AIOC master that generated the transaction).
5.5.2
IMCH - Memory Controller
The memory controller can notify the IA-32 core of memory-related error events
through SCI, SMI, SERR, or MCERR signals based on the settings in the
DRAM_SCICMD, DRAM_SMICMD, DRAM_SERRCMD, and DRAM_MCERRCMD registers
(see Section 11.0, “System Memory Controller”). Software can configure the specific
signal used for each error event independently.
Table 5-24 summarizes the error conditions that the memory controller captures. Note
that the memory controller always reports errors through the non-fatal classification in
the error reporting registers.
.
Table 5-24. Summary of Memory Controller Error Conditions
Event
Type
Fatality^a
Reports via^b
Notes
Uncorrectable
Write Error
Uncorrectable
Read Error
Uncorrectable
Scrubber Data
Error
Correctable Read
Error
Error Threshold
Detect
Memory Test
Complete
Uncorrectable
Uncorrectable
Uncorrectable
Correctable
Status
Status
Fatal
Fatal
Fatal
Non-Fatal
Non-Fatal
Non-Fatal
SCI, MCERR,
SMI, or SERR
Write of poisoned data to DRAM.
SCI, MCERR,
SMI, or SERR
Error during normal demand reads.
SCI, MCERR, Memory scrubber encountered an
SMI, or SERR uncorrectable error.
SCI, MCERR, Hardware will correct and report if
SMI, or SERR appropriately configured
SCI, MCERR, Count of single- or double-bit errors
SMI, or SERR exceeds a programmable threshold.
SCI, MCERR, Status event to indicate when memory
SMI, or SERR test hardware completes testing.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. This
can differ from the fatal/non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on DRAM_SCICMD, DRAM_SMICMD, DRAM_SERRCMD, and DRAM_MCERRCMD register values.
Table 5-25 summarizes the capabilities of the memory controller error handling for
each of the features that the unit is expected to provide.
Intel^® EP80579 Integrated Processor Product Line Datasheet
154
August 2009
Order Number: 320066-003US