EP80579 Datasheet, PDF (374/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 15-4. Command (CMD) Register (Sheet 2 of 2)
Bit
04
03: 02
01: 00
Description
Reserved - Set to 0.
Internal Command Size: All accesses are naturally aligned to the access width. This field specifies
the internal command to be issued by the SMBus slave logic to the IMCH core.
00 = Read Dword
01 = Write Byte
10 = Write Word
11 = Write Dword
SMBus Command Size: This field specifies the SMBus command to be issued on the SMBus. This
field is used as an indication of the length of the transfer so that the slave knows when to expect
the PEC packet (if enabled).
00 = Byte
01 = Word
10 = Dword
11 = Reserved
15.2.1.3.2
BYTCNT – Byte Count Register
The byte count register indicates the number of bytes following the byte count register
when performing a write or when setting up for a read. The byte count is also used
when returning data to indicate the following number of bytes (including the status
byte), which are returned prior to the data. Note that the byte count is only transmitted
for block type accesses on SMBus. SMBus word or byte accesses do not use the byte
count.
Table 15-5. Byte Count Register
Position
Description
07:00
Byte Count: Number of bytes following the byte count for a transaction.
15.2.1.3.3
ADDR3 – Address Byte 3 Register
This register must be programmed with the Bus Number of the desired configuration
register in the lower five bits for a configuration access. For a memory-mapped access
this field selects which memory-map region is being accessed. There is no status bit to
poll to see if a transfer is currently in progress, because by definition, if the transfer
completed, the task is done. The clock stretch is used to guarantee the transfer is truly
complete.
The EP80579 does not support access to other logical bus numbers via the SMBus port.
All registers “attached” to the configuration mechanism that the SMBus has access to,
reside on logical bus#0.
Table 15-6. Address Byte 3 Register
Position
07:05
04:00
Configuration Register Mode Description
Memory Mapped Mode Description
Ignored.
Bus Number: Must be zero: the SMBus port
can only access devices on the IMCH and all
devices are bus zero.
Memory map region to access.
00h = NSI
01h = EDMA
08h = DDR2
Others = Reserved
Intel^® EP80579 Integrated Processor Product Line Datasheet
374
August 2009
Order Number: 320066-003US