EP80579 Datasheet, PDF (1652/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.13 Offset 0030h: TS_ASMLo - Auxiliary Slave Mode Snapshot Low
Register
Register
Name
TS_ASMSLo
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASMS_Low[31:0]
Table 41-23. Offset 0030h: TS_ASMSLo Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000030h
Offset End: 00000033h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
31 : 0
Bit Acronym
Bit Description
Sticky
ASMS_Low
When the board is operating in Slave mode, the active
high level of a general-purpose input, asmssig, triggers a
snapshot of System Time into the ASMS_Low and
ASMS_High registers.
Note: The processor can configure the GPIO bit as an
output, but it will always be input-only to the Time Sync
block.
When the ASMS snapshot occurs, the sns indication in the
Time Sync Event register is set. Writing a logic 1 to that
bit clears the snapshot indication and allows a new
snapshot to occur on the next active high level of
asmssig.
Bit Reset
Value
0000h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1652
August 2009
Order Number: 320066-003US