EP80579 Datasheet, PDF (340/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.10.2.3 MSI Data Register – MSIDR
The MSI Data Register (MSIDR) contains routing and priority data for generation of MSI
interrupts.
12.10.3
Interrupt Ordering
To support MSI signaling as transfers complete, the IMCH must take special steps in
hardware to ensure that IA-32 core accesses to memory in response to MSI do not
experience producer/consumer ordering failures. Specifically, the chip must internally
guarantee functionality equivalent to a logical “FENCE” operation between the MSI and
subsequent IA-32 core traffic from the FSB.
12.10.3.1 Interrupt Ordering for Memory Destination
The failure to be prevented for interrupts signaled at the end of transfers to memory
destinations is as follows:
• Each EDMA channel is programmed to move a single cache-line of data and issue
an MSI upon completion. This is a special case, for illustrative purposes; a similar
scenario arises for the last few writes of a multi-line transfer.
• As soon as the write data is posted into the inbound/outbound arbiter headed for
the memory interface, the MSI is issued directly to the FSB. Note that the transfer
to memory may be issued without an accompanying FSB snoop cycle (non-
coherent), thus the data and interrupt message are logically traversing
independent traffic paths.
• In response to the MSI, the IA-32 core issues a memory read to retrieve the data
from memory. In the absence of an internal interlock, this read may proceed to the
memory controller before the posted write data is accepted into the memory
controller from the inbound/outbound arbiter. This is where the error occurs,
because the memory controller will not have any information regarding the relative
issue order of the write and the read – if the read gets there first, it will retrieve
stale data.
To prevent such a failure, the inbound/outbound arbiter includes specialized hardware
to guarantee that all posted write data received ahead of an MSI are forwarded out of
the arbiter before the MSI message will be forwarded to the FSB.
A similar interlock in the inbound/outbound arbiter prevents failures in the non-
interrupt case. When software is polling the Channel Status Register (CSR) to detect
transfer completion, specialized hardware guarantees that the read completion stalls
until all prior posted write data is forwarded out of the arbiter.
12.10.3.2 Interrupt Ordering for Outbound Destination
The failure to be prevented for interrupts signaled at the end of transfers to outbound
port destinations is as follows:
• Each EDMA channel is programmed for a single block transfer to an I/O device, with
interrupt notification enabled at the completion of that transfer. For this example,
MSI generation is disabled.
• When the final write of the transfer is posted into the inbound/outbound arbiter, a
level-sensitive interrupt is signaled directly to the interrupt output pin, bypassing
all internal queue structures.
• If the integrated IOxAPIC is enabled, the response to the interrupt pin will be an
APIC message received. If the APIC is disabled, a sideband interrupt is signaled
directly to the IA-32 core via a level sensitive output.
Intel^® EP80579 Integrated Processor Product Line Datasheet
340
August 2009
Order Number: 320066-003US