EP80579 Datasheet, PDF (832/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.2.5
Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register
The CT and RP values for the ATA_FAST (100MB/s and 133 MB/s modes) are based on
133 MHz clock. The CT and RP values for the 66 MHz and 33 MHz modes are based on
either a 66 MHz or 33 MHz clock.
Table 23-23. Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 4Ah
Offset End: 4Bh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 14
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
Secondary Device 1 Cycle Time (SCT1): The setting of
these bits determines the minimum write strobe cycle
time (CT) and DMARDY#-to-STOP (RP) time.
Bit Reset
Value
0h
Bit Access
RO
13 : 12
SCT1
SBC[3] = 0
Bits
CT
RP
00
4
6
01
3
5
10
2
4
11
Reserved
SBC[3] = 1 FSBCE[3] = 1
CT RP
Reserved
3
8
2
8
Reserved
CT RP
Reserved
3
16
Reserved
Reserved
00h
RW
11 : 10
09 : 08
07 : 06
05 : 04
03 : 02
01 : 00
Reserved
SCT0
Reserved
PCT1
Reserved
PCT0
Reserved
Secondary Device 0 Cycle Time (SCT0): Same
definition as bits 13:12, except for device 0.
Reserved
Primary Device 1 Cycle Time (PCT1): Same definition
as bits 13:12, except for primary device 1.
Reserved
Primary Device 0 Cycle Time (PCT0): Same definition
as bits 13:12, except for primary device 0.
0h
RO
00h
RW
0h
RO
00h
RW
0h
RO
00h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
832
August 2009
Order Number: 320066-003US