EP80579 Datasheet, PDF (102/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 1-4. Glossary Table (Sheet 5 of 5)
Term
Sx States
Simplex
SMBus
Snooping
South
South Port
Split Lock Sequence
Split Transaction
Symbol
Symbol Time
Target
Tenured Transaction
Transaction
Transaction Identifier
Transmitter
Upstream
VCMI
Definition
Sleeping states (Sx states) are types of sleeping states within the global sleeping state, G1.
• S5: Soft Off state. The main memory power plane is shut down in addition to the clock
synthesizer and core well power planes for the processor and CMI. The CMI resume well is
still powered.
• S4: Sleeping state - This state is only used to transition to or from the S5 state. The S4
state is not a supported power management state in CMI.
• S3: Suspend to RAM (STR) state - The clock synthesizer and core well power planes for the
processor and CMI are shut down, but the main memory power plane and the CMI resume
well remain active. All clocks from synthesizers are shut down during the S3 state.
• S0: Awake state - Power Management state when all power planes are active.
A connection or channel that allows data or messages to be transmitted in one direction only.
System Management Bus. A two-wire interface through which various system components may
communicate.
A means of ensuring cache coherency by monitoring all memory accesses on a common multi-
drop bus to determine if an access is to information resident within a cache.
Usually refers to bridges. The bridge or device that is further from the processor-memory
complex.
The PCI Express* downstream root port(s) on the IICH.
A sequence of transactions that occurs when the target of a lock operation is split across a
processor bus data alignment or Cache Line boundary, resulting in two read transactions and
two write transactions to accomplish a read-modify-write operation.
A transaction that consists of distinct Request and Completion phases or packets that allow use
of bus, or interconnect, by other transactions while the Target is servicing the Request.
An expanded and encoded representation of a data Byte in an encoded system (e.g., the 10b
value in a 8b/10b encoding scheme). This is the value that is transmitted over the physical
medium.
The amount of time required to transmit a symbol.
A device that responds to bus Transactions. The agent receiving a request packet is referred to
as the Target for that Transaction.
A transaction that holds the bus or interconnect until complete, effectively blocking all other
transactions while the Target is servicing the Request.
An overloaded term that represents an operation between two or more agents that can be
comprised of multiple phases, cycles, or packets.
A multi-bit field used to uniquely identify a transaction. Commonly used to relate a Completion
with its originating Request in a Split Transaction system.
1. The Agent that sends a Packet across an interface regardless of whether it was the original
generator of the packet. 2. More narrowly, the circuitry required to drive signals onto the
physical medium.
Describes commands or data flowing toward the processor-memory complex and away from I/
O. The terms Upstream and Downstream are never used to describe transactions as a whole.
(For example, Upstream data may be the result of an Inbound Write, or an Outbound Read.
The Completion to an Outbound Read travels Upstream.)
IA-32 core, IA-32 Core interface, Memory controller hub, I/O controller hub
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Intel^® EP80579 Integrated Processor Product Line Datasheet
102
August 2009
Order Number: 320066-003US