EP80579 Datasheet, PDF (312/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 12-3. Chain Descriptor in Memory
12.3.2
12.3.3
Chain Descriptor in Memory
Description
Source Address (SAR)
Source Upper Address
(SUAR)
Lower 32-bit Source Memory Address Register
Upper 32-bit Source Memory Address Register
Destination Address
(DAR)
Lower 32-bit Destination Memory Address Register
Destination Upper Address
(DUAR)
Upper 32-bit Address of Next Chain Descriptor Register
Next Descriptor Address
(NDAR)
Lower 32-bit Address of Next Chain Descriptor Register
Next Descriptor Upper Address
(NDAUR)
Upper 32-bit Address of Next Chain Descriptor Register
Transfer Count
(TCR)
Number of Bytes to Transfer Register
Descriptor Control
(DCR)
Descriptor Control Register
B4483-01
DMA Chain Descriptor in Memory
Each chain descriptor is composed of eight Dwords. Each Dword in the chain descriptor
in the local memory is analogous to the corresponding EDMA channel register value.
The bit definitions in the chain descriptor in memory are identical to those of the
corresponding channel register. Refer to the EDMA channel-specific register definitions
in “Memory Mapped I/O for EDMA Registers” on page 651 for descriptions of the fields
defined by a chain descriptor.
After a transfer has been requested, the EDMA channel reads the specified chain
descriptor from local system memory and updates its own corresponding channel
registers automatically.
Chain Descriptor Usage
A linked list of chain descriptors may be built in the local system memory to transfer
data within the local system memory or from local system memory to I/O subsystem
memory. An application may build multiple chain descriptors to transfer many blocks
with differing source addresses, destination addresses, data transfer counts,
alignments, and coherence attributes. The application may connect these chain
descriptors using the Next Descriptor Address in a sequence of chain descriptors,
creating a linked list of EDMA transfers, all of which may complete without any
processor intervention. Figure 12-4 shows a linked list of transfers built in local system
memory and illustrates how they are “chained” together.
Intel^® EP80579 Integrated Processor Product Line Datasheet
312
August 2009
Order Number: 320066-003US