EP80579 Datasheet, PDF (631/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.37.1 MBDATA Failure Address Mapping
To compress the failure address into 32 bits, bits that are always zero are removed
from the logging. These removed bits include AutoPrecharge Column address [10] and
least significant bits assumed by burst length.
Table 16-260.MBDATA Failure Address Register Correspondence to DRAM Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
see description below
Bank
Row
Column and Chunk
BL4: 1 bit chunk indicates the location of 2 failure burst data chunks.
The above Column plus Chunk is equal to DRAM column address as the following:
Table 16-261.BL4 Column and Chunk Correspondence to DRAM Address
Register Bit Location
12 11 10 9 8 7 6 5 4 3 2 1 0
DRAM Col Address
14 13 12 11 9 8 7 6 5 4 3 2
Data Chunk
1X
• Where the auto-precharge address bit 10 is assumed zero.
• Since data is logged in 144 bits (two chunks), address bit zero is not needed.
BL8: 2 bit chunk indicates the location of 4 failure burst data chunks.
The above Column plus Chunk is equal to DRAM column address as the following:
Table 16-262.BL8 Column and Chunk Correspondence to DRAM Address
Register Bit Location
12 11 10 9 8 7 6 5 4 3 2 1 0
DRAM Col Address
14 13 12 11 9 8 7 6 5 4 3
Data Chunk
2 1X
• Where the auto-precharge address bit 10 is assumed zero.
• Since data is logged in 144 bits (two chunks), Data chunk address bit zero is not
needed.
16.5.1.38 Offset 19Ch: MB_START_ADDR - Memory Test Start Address Register
MB_END_ADDR row and column address must be larger than MB_START_ADDR row
and column address in either increasing or deceasing address mode.
During FastX, FastY and FastXY operation, only one memory bank is tested. Specify the
desired bank in MB_START_ADDR[2:0]. MB_END_ADDR[2:0] is ignored.
In XZY address mode, bank address wraps around either in the 4 banks or 8 banks
case. In XZY mode, MB_END_ADDR bank address may be smaller than
MB_START_ADDR bank address.
This register is only used when MBCSR.atype = 2b’10, and when MBCSR.algo is non-
zero.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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