EP80579 Datasheet, PDF (297/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
11.3.4.1
Note:
2T Timing Mode
The address and command group (Bank Address BA[2:0], Address MA[14:0],
Command pins RAS_L, CAS_L and WE_L) of pins to the DRAM devices can be clocked
either by 1T or 2T timing as shown in Figure 11-3. The control group of pins (CKE, CS,
ODT) are not impacted by the 2T timing mode.
When in 1T timing mode, a new command can be issued to the DRAM devices every
DRAM clock cycle. In 2T timing mode, a new command can be issued to the DRAM
devices every other DRAM clock cycle i.e., the address and command bus needs to be
held valid for 2 cycles.
2T timing reduces the efficiency of the command bus by half but it doubles the setup
and hold time for the command and address bus. The timing for the DRAM data bus
and all other signals to the DRAM devices remain the same between 1T and 2T timing
modes.
On the EP80579, unbuffered dual DIMM configurations are supported in 2T timing
mode. Single DIMM configurations are supported in 1T timing mode. Please refer to
Table 11-5 for details. The 2T timing mode can be selected by setting the 2T or1T bit in
“Offset 64h: DRT1 – DRAM Timing Register 1”.
1T/2T timing is also referred to as 1N/2N timing.
Figure 11-3. 2T and 1T Timing Mode
CK
Control
Address /
Command
CK
Control
Address /
Command
2T Timing Mode
NOP
NOP
2 cycle Address/Command
1T Timing Mode
NOP
NOP
1 cycle Address/
Command
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
297