EP80579 Datasheet, PDF (1138/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.3.4.1
APIC_ID – Identification Register
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the
APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.
Table 30-26. APIC_ID – Identification Register
Description:
View: IA I
Win:Idx: APIC_WDW:APIC_IDX
Size: 32 bit
Default: 0000h
Bit Range
31 : 28
27 : 24
23 : 16
15
14
13 : 00
Bit Acronym
Bit Description
Reserved
AID
Reserved
Scratchpad
Reserved
Reserved
Reserved
APIC Identification: Software must program this
value before using the APIC.
Reserved
Scratchpad
Reserved.
Reserved
Offset Start: 00h (4B)
Offset End: 00h (4B)
Power Well: Core
Sticky
Bit Reset
Value
0h
Bit Access
0h
RW
0h
0h
RW
0h
0h
30.3.4.2
APIC_VS - Version Register
Each I/O APIC contains a hardwired Version Register that identifies different
implementation of APIC and their versions. The maximum redirection entry information
also is in this register, to let software know how many interrupt are supported by this
APIC.
Table 30-27. APIC_VS - Version Register (Sheet 1 of 2)
Description:
View: IA I
Win:Idx: APIC_WDW:APIC_IDX
Offset Start: 01h (4B)
Offset End: 01h (4B)
Size: 32 bit
Default: 00170020h
Power Well: Core
Bit Range
31 : 24
23 :16
Bit Acronym
Bit Description
Sticky
Reserved
MRE
Reserved
Maximum Redirection Entries: This is the entry
number (0 being the lowest entry) of the highest entry
in the redirection table. This field reports either 17h or
27h depends on the value of GPIO_IRQ_STRAP_STS
field of Extended Test Mode Register3 register.
• 17h (to indicate 24 interrupts), when
ETR3.GPIO_IRQ_STRAP_STS = 0
• 27h (to indicate 40 interrupts), when
ETR3.GPIO_IRQ_STRAP_STS = 1 (siu2_txd_ad18
strap configuration)
Bit Reset
Value
0h
17h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1138
August 2009
Order Number: 320066-003US