EP80579 Datasheet, PDF (1715/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
44.0 IA-32 Core
The testability features supported by the IA-32 core integrated into Intel^® EP80579
Integrated Processor are described in this section.
44.1
JTAG
The IA-32 core TAP (Test Access Port) complies with the IEEE 1149.1 (“JTAG”) test
architecture standard. The TAP implements an instruction set of 6 functions as follows:
• SAMPLE/PRELOAD
• EXTEST
• CLAMP
• HIGHZ
• IDCODE
• BYPASS
44.1.1
Usage
There are seven 1149.1-defined public instructions implemented in the IA-32 core TAP.
These instructions are described in Table 44-1. These instructions select from among
three different TAP data registers — the boundary scan, device ID, and bypass
registers.
Table 44-1. 1149.1 Public Instructions in the IA-32 Core TAP
TAP
Instruction
(op-code)
Function
during
StopClk
Data
Register
Selected
Action during...
RT/IDLE Capture-DR
Shift-DR
Update-DR
SAMPLE/
PRELOAD
Yes
(0000001)
EXTEST
(0000000)
Yes
CLAMP
(0000100)
Yes
HIGHZ
(0001000)
Yes
IDCODE
(0000010)
Yes
BYPASS
(1111111)
Yes
Boundary
scan
Boundary
scan
Bypass
Bypass
Device ID
Bypass
—
Sample all IA-
32 core pins
Shift bscan
reg
Update bscan
reg. outputs
—
Sample all IA-
32 core pins
Shift bscan
reg
Update IA-32
core outputs
—
Reset bypass
reg
Shift bypass
reg
—
—
Reset bypass
reg
Shift bypass
reg
—
—
Load IA-32
core ID code
Shift ID reg
—
—
Reset bypass
reg
Shift bypass
reg
—
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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