EP80579 Datasheet, PDF (1551/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.7.3.2
37.7.3.3
37.7.3.4
37.7.4
D0u State
The D0u state is a low-power state used after UNIT_RESET is deasserted, or when
coming out of D3, but before the GbE Controller is initialized.
When entering D0u the GbE Controller will disable Wake Ups, assert reset to the PHY
for between 24µs and 1ms, and re-read the EEPROM. If the APM Mode bit in the
EEPROM's Initialization Control Word 2 is set then APM Wake Up will be enabled.
On a transition from D3 to D0u state, all of the PCI Configuration space is
reset. Per the PCI Power Management Specification (revision 1.1, section 5.4),
software “will need to perform a full reinitialization of the function including its PCI
Configuration Space.”
Internally, D0u is treated like D3 and some internal clocks and registers are shut down.
As in the Dr state, the PHY power state depends on whether PHY power-management
and WakeUp are enabled.
The D0u state is exited when the system enables memory space access to the
controller by writing a 1 to the Memory Access Enable bit of the PCI Command Register.
D0a
Once memory space is enabled all internal clocks are activated and the controller
enters an active state. It can transmit and receive packets if properly configured by the
driver. Any APM Wakeup previously active will remain active. The driver can deactivate
APM Wakeup by writing to the Wake Up Control Register (WUC), or activate other Wake
Up Filters by writing to the Wake Up Filter Control Register (WUFC).
D3
Prior to transition from D0 to the D3 state, the driver must ensure that controller
transmit and receive operation has been disabled and all pending bus transactions are
complete or terminated cleanly. If wake up capability is needed the driver should set up
the appropriate wake up registers and the system should write a 1 to the PME_En bit of
the Power Management Control / Status Register (PMCSR) prior to the transition to D3.
When the system writes a '11 to the PowerState field of the Power Management
Control/Status Register (PMCSR) the GbE controller will transition to D3. Any WakeUp
filter settings that were enabled before entering this reset state will be maintained.
Upon transitioning to D3 the controller will clear the Memory Access Enable bit of the
PCI Command Register, which will disable memory access decode.
For power savings, the GbE controller shuts down some internal clocks and registers in
D3 state.
To transition back to D0u, the system writes a 00 to the Power State field of the Power
Management Control/Status Register (PMCSR).
Timing of Power-State Transitions
The following sections give detailed timing for the state transitions. In the diagrams the
dotted connecting lines represent the MACs’ requirements, while the solid connecting
lines represent the MACs’ guarantees.
The timing diagrams are not to scale. The clocks edges are shown to indicate running
clocks only are not used to indicate the actual number of cycles for any operation.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1551