EP80579 Datasheet, PDF (1737/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
48.4.1.3 Sideband Miscellaneous Signals
Table 48-6. Sideband Miscellaneous Signals (Sheet 1 of 2)
Signal Name
CPUSLP_OUT#
INIT33V_OUT#
NMI
SMI_OUT#
IO Type
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
Direction
Ball
Count
O
1
O
1
I/O
1
O
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
BSC
BSC
BSC
CPU Sleep: This EP80579 output signal is made
visible to the platform for debug purposes only.
This internal EP80579 signal places the
processor into a state that saves substantial
power compared to the Stop-Grant state. When
EP80579 is in this state, it will not recognize
snoops or interrupts. The processor will
recognize only assertion of the CPURST# signal,
and deassertion of CPUSLP_OUT# while in Sleep
state. If CPUSLP_OUT# is deasserted, the
processor exits Sleep state and returns to Stop-
Grant state, restarting its internal clock signals
to the bus and processor core units.
CPU Initialization: This 3.3V EP80579 output
signal is made visible to the platform to reset
the Firmware Hub. Internal EP80579 signal that
when asserted, resets integer registers inside
the processor without affecting its internal
caches or floating-point registers. The processor
then begins execution at the power-on Reset
vector configured during power-on
configuration. The processor continues to handle
snoop requests during INIT33V_OUT#
assertion. INIT33V_OUT# is an asynchronous
signal. However, to ensure recognition of this
signal following an Input/Output Write
instruction, it must be valid along with the
TRDY# assertion of the corresponding Input/
Output Write bus transaction.
Non-Maskable Interrupt: NMI is used to force a
non-maskable interrupt to the processor, if
configured. The processor detects an NMI as a
rising edge on NMI. NMI is reset by setting the
corresponding NMI source enable/disable bit in
the NMI Status and Control Register (I/O
Register 61h), except when an external platform
agent is driving the NMI pin.
System Management Interrupt: This EP80579
output signal is made visible to the platform for
debug purposes only. This internal EP80579
signal is active low output synchronous to
PCICLK that is asserted in response to one of
many enabled hardware or software events. On
accepting a System Management Interrupt, the
processor saves the current state and enter
System Management mode (SMM). An SMI
Acknowledge transaction is issued, and the
processor begins program execution from the
SMM handler.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1737