EP80579 Datasheet, PDF (172/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 6-4. Power Rail Sequence Signal Timings
Sym
Parameter
Min
Max
Units
Notes
t210
Core 3.3 V active to Core 2.5 V active
0
–
ms
5
t211
Core 2.5 V active to Core 1.2 V active
0
ms
6
t212
Suspend supplies active to Core supplies active
0
–
ms
4
t213
All core supplies active to SYS_PWR_OK (platform signal) active
99
–
ms
NOTES:
1. The 5 V supply must power up before its associated 3.3 V supply within 0.3 V, and must power down after the 3.3 V supply
within 0.3V.
2. Ensure the following: a) Suspend 3.3 V must power up before Suspend 2.5 V or after Suspend 2.5 within 0.3 V, b) Suspend
2.5 V must power down before Suspend 3.3 V or after Suspend 3.3 V within 0.3 V.
3. Ensure the following: a) Suspend 2.5 V must power up before Suspend 1.2 V or after Suspend 1.2 V within 0.3 V, b) Suspend
1.2 V must power down before Suspend 2.5 V or after Suspend 2.5 V within 0.3 V.
4. The VccSus supplies must never be active while the VCCPRTC supply is inactive.
5. Ensure the following a) Core 3.3 V must power up before Core 2.5 V or after Core 2.5 V within 0.3 V, b) Core 2.5 V must
power down before Core 3.3 V or after Core 3.3 V within 0.3 V.
6. Ensure the following: a) Core 2.5 V must power up before Vcc1.2 V or after Core 1.2 V within 0.3 V, b) Core 1.2 V must power
down before Core 2.5 V or after Core 2.5 V within 0.3 V.
Figure 6-6. Powergood Reset Sequence
Power Rails
BSEL
CPU+VRD_PWR_GD/
VRMPWRGD
Reference Clock
SYS_PWR_OK/
PWROK/PWRGD
CPU_PWRGD
PLTRST#/RSTIN#
PCIRST#
CPU Power-On
Configuration
CPURST#
ab
cd
f
ij
B6548-01
Intel^® EP80579 Integrated Processor Product Line Datasheet
172
August 2009
Order Number: 320066-003US