EP80579 Datasheet, PDF (1890/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 49-81. EEPROM Read Operation (Sheet 2 of 2)
Step
5
6
7
Parameter
An internal pullup is implemented on the EEDO pin so the pin initially floats high. When the EEPROM
latches its last address bit it drives EEDO low. This can be used during the initial read to determine
the size of the EEPROM. A 64-word EEPROM drives "data out" low after 6 address bits, while a 256-
word EEPROM drives "data out" low after 8 address bits.
After driving its "data out" low, the EEPROM device drives 16 data bits, starting at the most significant
bit. Each bit is driven after the rising edge of the clock.
After the read cycle, the EP80579 stops driving the clock and deasserts the chip select. When the chip
select is deasserted the EEPROM stops driving the data.
Table 49-82. EEPROM Timing Values
Symbol
Parameter
Min
Max
Units Figure Notes
tcs
Chip select to first clock edge.
1024
3048
ns
49-42
1
tck
EEPROM clock cycle
1024
4160
ns
49-42
1
tsu
Setup time before rising clock edge.
480
-
ns
49-42
1
th
Hold time after rising clock edge.
480
-
ns
49-42
1
tcsl
Chip select deassertion time
992
-
ns
49-42
1
Notes:
1.
Guaranteed by design. These values are typical values seen for this process, but not measured during
production testing.
49.5.13.4 GbE Reset Conditions
There is no special reset sequence required for GbE I/O buffers. GbE receives a power-
on reset signal from the CRU, but drives input data present on the input pins into the
core during reset. Core logic forces all outputs to High-Z during reset.
49.5.13.5 RComp
The GbE RCOMP (resistive compensation) circuitry dynamically compensates the
GbE I/O output drivers for variations in operating conditions due to process,
temperature, voltage and PCB layout. These variations are measured through a
resistive mechanism in two special I/O pads. The resistive mechanism on those I/O
pads reference external resistors that the user provides to match output driver
strength. Thus the output driver impedance can be tuned specifically to the application
PCB characteristics for nominal signal transfer into the transmission lines formed by the
PCB traces. The RCOMP design is nominally set to operate at 50 ohm, but the user is
free to set the impedance in the range 45 ohm to 55 ohm.
Two RCOMP pins are provided to establish the GbE output driver impedance, one to
control the drive high strength, and one to control the drive low strength. These RCOMP
outputs drive into external resistors. The drivers form a resistor divider and the
voltages developed in these dividers are compared to a reference voltage. The RCOMP
state machine independently adjusts the strength of the drivers making them stronger
or weaker until the comparator signals that the voltage is greater than or less than the
reference. The state machine continues making adjustments causing the comparators
to oscillate between two strength settings just above and just below the comparator
trip point. Logic in the RCOMP state machine recognizes when this "dithering" between
the two values has begun, and holds the strength output for the GbE outputs fixed at
one of the two settings. Note this algorithm is independently and concurrently applied
to the drive high strength and to the drive low strength.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1890
August 2009
Order Number: 320066-003US