EP80579 Datasheet, PDF (764/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.2
Note:
LPC DMA I/O-Mapped Register Details
Some registers are normally read-only, but are writable in Alt-Access mode. Likewise,
there are some registers that are normally write-only, but are readable in Alt-Access
mode. The individual register descriptions may not indicate this. See Alt-Access mode
for more details.
Table 20-1. Summary of LPC DMA Registers Mapped in I/O Space
Offset Start Offset End
Register ID - Description
Default
Value
00h at 02h
10h at 02h
“Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address Registers for
Channels 0-3” on page 766
XXXX
C4h at 04h
C5h at 04h
“Offset C4h: DMA_BCA[5-7] - DMA Base and Current Address Registers for
Channels 5-7” on page 767
XXXX
01h at 02h
11h at 02h
“Offset 01h: DMA_BCC[0-3] - DMA Base and Current Count Registers for Channels
0-3” on page 768
XXXX
C6h at 04h
C7h at 04h
“Offset C6h: DMA_BCC[5-7] - DMA Base and Current Count Registers for Channels
5-7” on page 769
XXXX
87h, 83h,
81h, 82h
97h, 93h,
91h, 82h
“Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels 0-3”
on page 771
XXXXXXX
8Bh, 89h, 8Ah
9Bh, 99h, 9Ah
“Offset 8Bh: DMA_MPL[5-7]: DMA Memory Low Page Registers for Channels 5-7”
on page 771
XXXXXXX
Table 20-2. 0000h (IO) Base Address Registers in the IA F1 View
Offset Start Offset End
Register ID - Description
08h
18h
08h
18h
0Ah
1Ah
0Bh
1Bh
0Ch
1Ch
0Dh
1Dh
0Eh
1Eh
0Fh
1Fh
08h
18h
08h
18h
0Ah
1Ah
0Bh
1Bh
0Ch
1Ch
0Dh
1Dh
0Eh
1Eh
0Fh
1Fh
“Offset 08h: DMA_COMMAND - DMA Command Register” on page 770
“Offset 08h: DMA_COMMAND - DMA Command Register” on page 770
“Offset 08h: DMA_STATUS - DMA Status Register” on page 772
“Offset 08h: DMA_STATUS - DMA Status Register” on page 772
“Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773
“Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773
“Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774
“Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774
“Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775
“Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775
“Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775
“Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775
“Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776
“Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776
“Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777
“Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777
Default
Value
000X0X00b
000X0X00b
XXXXXXXh
XXXXXXXh
000001xxb
000001xxb
000000XXh
000000XXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
00001111b
00001111b
Intel^® EP80579 Integrated Processor Product Line Datasheet
764
August 2009
Order Number: 320066-003US