EP80579 Datasheet, PDF (89/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Revision History
Date
August
2009
Revision Description
Added:
• Industrial temperatures to Chapter 49.0, “Electrical Specifications” and Chapter 50.0, “Thermal
Specifications and Design Considerations”
The following changes were made due to defeaturing LEB Mastering:
• Section 2.2, “Signaling Architecture”
• Table 2-1, “EP80579 External Interface Summary” - LEB Description
• Table 2-4, “Summary of Communication” - removed “LEB Master”
• Table 3-7, “Address Space Sizes of AIOC-attached Devices” - removed LEB row
• Note E in Table 3-11, “PCI Configuration Header Support for Type 0 Headers in AIOC Devices”
• Section 4.2.2, “Other Agents” - fourth bullet removed “master”
• Table 5-32, “Summary of Local Expansion Bus Error Conditions” - Notes description
• Removed rows in Table 7-67, “Bus M, Device 8, Function 0: Summary of Local Expansion Bus
Registers Mapped Through CSRBAR PCI Memory BAR"” containing LEB content
003
• Removed LEB content from Section 36.3, “Local Expansion Bus Interface (LEB)”
• Removed content from Section 42.0, “Local Expansion Bus Controller”
•“EXP_MST_CONTROL - Expansion Bus Control Register”
•“EXP_LOCK0 - Expansion Bus Lock Register”
•“Offset D0500010h: CMD_TRNS1_W[0-3] - Command Translation Window Register “
• Removed LEB content from Section 42.1, “Overview” and Section 42.2, “Feature List”
• Removed LEB content from Figure 42-1, “Expansion Bus Controller”
• Removed LEB content and also “Inbound Transfers” , “Arbitration”, “Expansion Bus Inbound Timing
Diagrams” and “External Expansion Bus Timing Diagram” content from Section 42.4, “Theory of
Operation”
• Removed Table 42-16 and Section 42.5.2.6
Removed:
Removed two rows with D30/D31 content from Table 1-4, Section 6.1.2.3.1, “IICH”, Table 28-9, and
from PCIRST# description in Table 48-28.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
89