EP80579 Datasheet, PDF (429/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 6 of 7)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 78h
Offset End: 7Bh
Size: 32 bit
Default: 242AD280h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
CAS# Latency: The number of clocks between the rising
edge used by DRAMS to sample the Read Command and
the rising edge that is used by the DRAM to drive read
data.
DDR2 JEDEC Spec: Write latency (WL) is defined by a read
latency (RL) minus one. Please refer to the DDR2 JEDEC
Spec for more details.
Bit Reset
Value
Bit Access
5 :03
CL
Encoding
000
001
010
011
Others
Number of
CMDCLK
delays
3
4
5
6
Reserved
N
000b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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