EP80579 Datasheet, PDF (698/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
17.1.3
17.1.3.1
Internal Link Configuration Registers
Offset 01A0h: ILCL - Internal Link Capabilities List Register
Table 17-15. Offset 01A0h: ILCL - Internal Link Capabilities List Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 01A0h
Offset End: 01A3h
Size: 32 bit
Default: 00010006h
Power Well: Core
Bit Range
31 :20
19 :16
15 :00
Bit Acronym
Bit Description
Sticky
NEXT
CV
CID
Next Capability: Indicates this is the last item in the list.
Capability Version: Indicates the version of the
capability structure.
Capability ID: Indicates this is the capability for NSI.
Bit Reset
Value
000h
1h
0006h
Bit Access
RO
RO
RO
17.1.3.2 Offset 01A4h: LCAP - Link Capabilities Register
Table 17-16. Offset 01A4h: LCAP - Link Capabilities Register (Sheet 1 of 2)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 01A4h
Offset End: 01A7h
Size: 32 bit
Default: 0012441h
Power Well: Core
Bit Range
31 :18
17 :15
14 :12
Bit Acronym
Bit Description
Sticky
Reserved
EL1
EL0
Reserved
The EP80579 does not support L0s or L1.
L1 Exit Latency: Indicates that the exit latency is 2 µs to
4 µs.
The EP80579 does not support L0s or L1.
L0s Exit Latency: This field is read/write and updatable
by BIOS. It defaults to 128 ns to less than 256 ns,
assuming a common-clock configuration between IICH
and IMCH. If a unique clock value is used, it is
recommended that BIOS update this field to 100 (512 ns
to less than 1 µs).
When BIOS set sets this field, it must also update NSI's
DBG.NFTS field, located at offset 2024h in configuration
space.
Bit Reset
Value
0h
010b
010b
Bit Access
RO
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
698
August 2009
Order Number: 320066-003US